1. Field of the Invention
The present invention generally relates to mounting methods of semiconductor elements and manufacturing methods of semiconductor devices, and more specifically, to a mounting method of a semiconductor element wherein the semiconductor element is mounted on a wiring board via an outside connection projection electrode not containing lead (Pb) and a manufacturing method of a semiconductor device.
2. Description of the Related Art
Conventionally and continuing to the present, a semiconductor device having a structure where a semiconductor element is flip chip mounted on a wiring board in a face-down manner via an outside connection projection electrode not containing lead (Pb), called a lead-free solder bump, is known.
FIG. 1 is a cross-sectional view showing a structure of a semiconductor element applied to such a semiconductor device. FIG. 2 is an enlarged view of a part surrounded by a dotted line in FIG. 1.
Referring to FIG. 1 and FIG. 2, for manufacturing the semiconductor element, a so-called wafer process is applied to a semiconductor substrate 1 made of silicon (Si). An active element such as a transistor or a passive element such as a capacitor (not shown) is formed on a main surface of the semiconductor substrate 1. In addition, a multilayer interconnection layer 3 is provided on another main surface of the semiconductor substrate 1 via an insulation layer such as a silicon oxide (SiO2) layer 2.
As shown in FIG. 2, such a multilayer interconnection layer 3 is formed by stacking plural wiring layers 4 made of aluminum (Al) or copper (Cu) via interlayer isolation films 5. Upper and lower wiring layers 4 are connected by an interlayer connection part.
As a material of the interlayer isolation film 5, so-called Low-K material, namely a material having a low dielectric constant, such as FSG (Fluorine Doped Silicon Glass) that is silicon glass doped with fluoride, SiOC that is silicon oxide where carbon is added, or an organic resin is used, so that the electric capacitance formed in wirings is reduced and the transferring speed of an electric signal is made high.
Functional elements such as the active elements or the passive elements formed on the semiconductor substrate 1 are connected to each other via the multilayer interconnection layer 3, so that an electronic circuit that performs a desirable function is formed.
Plural electrode pads 11 made of aluminum (Al) are selectively provided on upper parts of the multilayer interconnection layer 3 so as to be connected to the wiring 4 forming the multilayer interconnection layer 3.
A passivation layer 6 is selectively provided on the multilayer interconnection layer 3. The passivation layer 6 is made of an inorganic insulation material such as silicon oxide (SiO2) or silicon nitride (SiN). Openings are selectively formed in the passivation layer 6 so that center parts of the electrode pads 11 are exposed.
In addition, in order to protect a surface of the semiconductor element, an organic insulation film 7 is provided so as to cover an upper surface of the inorganic insulation layer 6 and an edge surface of the inorganic insulation layer 6 on the electrode pad 11.
A material of the organic insulation film 7 is selected from organic insulation material such as polyimide, BCB (Benzo-Cyclo-Butene), phenolic resin or polybenzoxazole.
A UBM (Under Bump Metallization) 8 made of, for example, titanium (Ti)/copper (Cu) is provided on an upper surface of the electrode pad 11. The UBM 8 is provided in a vertical direction from a part of the upper surface of the electrode pad 11 where the inorganic insulation layer 6 and the organic insulation film 7 are not provided to a position slightly above the upper surface of the organic insulation film 7. The UBM 8 covers an end surface of the organic insulation film 7.
Outside connection projection electrodes 9 having substantially spherical shape configurations are provided on the upper surface of the UBM 8. The outside connection projection electrode 9, called a solder bump, is made of a solder not containing lead (Pb) such as tin (Sn)—silver (Ag) or tin (Sn)—silver (Ag) including copper (Cu).
FIG. 3 is a cross-sectional view showing a state where the semiconductor element 10 shown in FIG. 1 is flip chip mounted on a wiring board. Referring to FIG. 3, the semiconductor element 10 is flip chip mounted face down on a wiring board 20.
The wiring board 20 is an organic buildup board made of, for example, glass epoxy material or polyimide tape. On an upper surface of the wiring board 20, plural electrode pads 21 are selectively provided and solder resist 22 is provided with selective openings so that center parts of the electrode pads 21 are exposed.
The outside connection projection electrodes 9 are connected to the electrode pads 21 provided on the wiring board 20. In addition, so-called underfill material 23 is provided between the semiconductor element 10 and the wiring board 20. Plural outside connection projection electrodes 24 made of solder are provided on a lower surface of the wiring board 20.
The semiconductor device having such a structure is manufactured by the following steps.
First, the semiconductor element 10 is flip chip mounted on the wiring board 20 in the face down manner.
Then, by a reflow heating process, the outside connection projection terminals 9 and preliminary solder (solder pre-coat) provided on the electrode pads 21 of the wiring board 20 in advance are made molten so that the outside connection projection terminals 9 of the semiconductor element 10 and the wiring board 20 are connected. The preliminary solder does not contain lead (Pb).
After that, the underfill material 23 is supplied between the semiconductor element 10 and the wiring board 20 and then cured.
Last, solder balls are provided on a lower surface of the wiring board 20 so that outside connection projection electrodes 24 are connected via a reflow heating process and a cooling process.
In the meantime, Japanese Laid-Open Patent Application Publication No. 2006-111898 discloses an electronic component having the following structure. That is, a tin-plated film on a base metal is subjected to oxidation or hydration treatment at room temperature, and a surface layer of an oxide or a hydroxide is formed on the surface of the tin-plated film so that the surface layer is dense and uniform, and suppresses the growth of tin whiskers.
Furthermore, Japanese Laid-Open Patent Application Publication No. 11-354919 discloses a manufacturing method of an electronic circuit board wherein an electronic component and the circuit board are connected by using lead (Pb) free solder including bismuth (Bi). In this method, the solder is cooled at a cooling speed of approximately 10-20° C./s so that the electronic component and the circuit board are connected.
In addition, International Patent Publication No. 2004/047167 discloses a semiconductor device wherein a through-electrode is formed in a wiring board so as to electrically connect a wiring layer formed on a wiring layer formation surface of a base substrate of the wiring board where a semiconductor chip is flip chip mounted and an electrode formed on a chip mounting surface; and the thermal expansion coefficient of the base substrate is equal to the thermal expansion coefficient of the semiconductor chip, or less than the thermal expansion coefficient of the wiring layer.
As discussed above, in manufacturing the semiconductor device wherein the semiconductor element 10 is flip chip mounted on the wiring board 20 via the outside connection projection electrode 9 not containing lead (Pb), by the reflow heating process, the outside connection projection terminals 9 and the preliminary solder (solder pre-coat) not containing lead (Pb) and provided on the electrode pads 21 of the wiring board 20 in advance are made molten, so that the outside connection projection terminals 9 of the semiconductor element 10 and the wiring board 20 are connected. After that, the outside connection projection terminals 9 and the preliminary solder are cooled so as to be made solid.
The coefficient of thermal expansion of a silicon substrate of the semiconductor element 10 is approximately 3 through 4 ppm/° C. On the other hand, the coefficient of thermal expansion of the wiring board 20 made of an organic material board is approximately 10 through 17 ppm/° C. Thus, the coefficient of thermal expansion of the wiring board 20 is greater than the coefficient of thermal expansion of the semiconductor element 10.
In addition, the outside connection projection terminals 9 and the preliminary solder are made of solder not containing lead (Pb). If the outside connection projection terminals 9 and the preliminary solder are made of, for example, solder formed by tin (Sn)—silver (Ag) or solder formed by tin (Sn)—silver (Ag)—copper (Cu), the melting point of the solder is approximately 217 through 220° C.
Therefore, in a state where the solder is heated to a temperature higher than the melting point such as 250° C., the solder is melted so as to follow deformation due to thermal expansion of the semiconductor element 10 and the wiring board 20.
In the reflow heating process, the wiring board 20 where the semiconductor elements 10 are provided is moved into a reflow processing apparatus where plural heating areas (blocks) have heaters are arranged in a line, so as to be processed. The temperature of the heaters in every heating area in the reflow processing apparatus is controlled so that the heating process and temperature decreasing process, namely cooling process, are performed.
FIG. 4 is a graph showing temperature change of the semiconductor device shown in FIG. 3 in a reflow heating process for connecting the outside connection projection electrodes 9 of the semiconductor element 10 and the wiring board 20 and a cooling process at a cooling rate of approximately 0.7° C./s after the reflow heating process. The horizontal axis of this graph indicates time (sec) and the vertical axis of this graph indicates temperature (° C.).
In other words, in the reflow heating process, a temperature of approximately 150° C. is maintained for a designated time. Flux is activated and oxide films on surfaces of the outside connection projection terminals 9 and the preliminary solder are removed. After that, heating is applied until the temperature is greater than the melting point of the solder, such as 250° C.
After the solder is molten, heating is stopped or the temperature is decreased to be equal to or lower than the melting point of the solder (217 through 220° C.) and thereby the solder is made solid. After the solder is solidified, cooling is gradually applied from the melting point of the solder to a temperature near normal room temperature.
In the related art, for efficiency of manufacturing steps, approximately 0.7° C./s is applied as a cooling rate. As discussed above, the melting point of the solder not containing lead (Pb) is higher than the melting point of the solder containing lead (Pb). Therefore, for efficient cooling to a temperature near normal temperature, the cooling rate of approximately 0.7° C./s is applied in the related art.
However, if the semiconductor device is cooled at the cooling rate of approximately 0.7° C./s, based on difference of coefficients of thermal expansion between the semiconductor element 10 and the wiring board 20, strain/stress is remarkably generated. In other words, since the coefficient of thermal expansion of the wiring board 20 is greater than the coefficient of thermal expansion of the semiconductor element 10, stress is applied from the wiring board 20 having greater expansion and contraction due to the temperature change to the semiconductor element 10 at the time of the cooling process.
Since such a state is generated when the solder (the outside connection projection terminals 9 and the preliminary solder) is solid, it is not possible for the solder to absorb the stress applied from the wiring board 20 to the semiconductor element 10. Therefore, the stress applied from the wiring board 20 to the semiconductor element 10 may be applied to the interlayer insulation film 5 made of the Low-K material of the multilayer wiring layer 3.
As a result of this, delamination of the wiring layers 4 stacked on each other via the interlayer insulation films 5 may be generated so that electrical defects may occur in the semiconductor device.